·         512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.

·         98 kB on-chip SRAM includes:

o   64 kB of SRAM on the ARM local bus for high performance CPU access.

o   16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

o   16 kB SRAM for general purpose DMA use also accessible by the USB.

o   2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

·         Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.

·         EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM.

·         Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

·         General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.

·         Serial Interfaces:

o   Ethernet MAC with MII/RMII interface and associated DMA controller. These

o   functions reside on an independent AHB bus.

o   USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and

o   associated DMA controller.

o   Four UARTs with fractional baud rate generation, one with modem control I/O, one

o   with IrDA support, all with FIFO.

o   CAN controller with two channels.

o   SPI controller.

o   Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

o   for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

o   Three I2C-bus interfaces (one with open-drain and two with standard port pins).

o   I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

o   the GPDMA.

·         Other peripherals:

o   SD/MMC memory card interface.

o   160 General purpose I/O pins with configurable pull-up/down resistors.

o   10-bit ADC with input multiplexing among 8 pins.

o   Four general purpose timers/counters with 8 capture inputs and 10 compare

o   outputs. Each timer block has an external count input.

o   Two PWM/timer blocks with support for three-phase motor control. Each PWM has

o   an external count inputs.

o   RTC with separate power domain, clock source can be the RTC oscillator or the

o   APB clock.

o   2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

o   rest of the chip is powered off.

o   WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

o   the RTC oscillator, or the APB clock.

·         Standard ARM test/debug interface for compatibility with existing tools.

·         Emulation trace module supports real-time trace.

·         Single 3.3 V power supply (3.0 V to 3.6 V).

·         Three reduced power modes: idle, sleep, and power-down.

·         Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources.

·         Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).

·         Two independent power domains allow fine tuning of power consumption based on needed features.

·         Each peripheral has its own clock divider for further power saving. These dividers help reducing active power by 20 – 30 %.

·         Brownout detect with separate thresholds for interrupt and forced reset.

·         On-chip power-on reset.

·         On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

·         4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run.

·         On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

·         Boundary scan for simplified board testing.

·         Versatile pin function selections allow more possibilities for using on-chip peripheral functions.